A25L80PQ-UF(2007) Ver la hoja de datos (PDF) - AMIC Technology
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A25L80PQ-UF
(Rev.:2007)
(Rev.:2007)
AMIC Technology
A25L80PQ-UF Datasheet PDF : 37 Pages
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Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select ( S ) Low.
The instruction code for the Read Data Bytes at Higher
Speed (FAST_READ) instruction is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then the
memory contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a maximum
frequency fC, during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9. The first byte
addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher
A25L80P Series
Speed (FAST_READ) instruction. When the highest address
is reached, the address counter rolls over to 000000h,
allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ)
instruction is terminated by driving Chip Select ( S ) High.
Chip Select ( S ) can be driven High at any time during data
output. Any Read Data Bytes at Higher Speed (FAST_READ)
instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle
that is in progress.
Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction
24-Bit Address
D
23 22 21 3 2 1 0
MSB
High Impedance
Q
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
D
7654 3 21 0
Data Out 1
Data Out 2
Q
76543210 765432107
MSB
MSB
MSB
Note: Address bits A23 to A20 are Don’t Care.
(April, 2007, Version 1.5)
14
AMIC Technology Corp.
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