A25L040N-U Ver la hoja de datos (PDF) - AMIC Technology
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A25L040N-U Datasheet PDF : 41 Pages
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A25L016 Series
Table 5. Protection Modes
W SRWD
Signal Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area1
Unprotected Area1
1
0
Status Register is Writable (if the Protected against Page
Ready to accept Page
Software WREN instruction has set the
Program, Dual Input Fast Program, Dual Input Fast
0
0
Protected WEL bit) The values in the
Program, Sector Erase,
Program, Sector Erase,
(SPM) SRWD, TB, BP2, BP1, and BP0 Block Erase, and Chip
and Block Erase
1
1
bits can be changed
Erase
instructions
0
1
Hardware
Protected
(HPM)
Status Register is Hardware write
protected The values in the
SRWD, TB, BP2, BP1, and BP0
bits cannot be changed
Protected against Page
Program, Dual Input Fast
Program, Sector Erase,
Block Erase, and Chip
Erase
Ready to accept Page
Program, Dual Input Fast
Program, Sector Erase,
and Block Erase
instructions
Note: 1. As defined by the values in the Block Protect (TB, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
The protection features of the device are summarized in Table
5.
When the Status Register Write Disable (SRWD) bit of the
Status Register is 0 (its initial delivery state), it is possible to
write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction, regardless of the whether Write Protect
( W ) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the
Status Register is set to 1, two cases need to be considered,
depending on the state of Write Protect ( W ):
If Write Protect ( W ) is driven High, it is possible to write
to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write
Enable (WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to
write to the Status Register even if the Write Enable Latch
(WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status
Register are rejected, and are not accepted for execution).
As a consequence, all the data bytes in the memory area
that are software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register, are also
hardware protected against data modification.
Regardless of the order of the two events, the Hardware
Protected Mode (HPM) can be entered:
by setting the Status Register Write Disable (SRWD) bit
after driving Write Protect ( W ) Low
or by driving Write Protect ( W ) Low after setting the
Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM)
once entered is to pull Write Protect ( W ) High.
If Write Protect ( W ) is permanently tied High, the Hardware
Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
(April, 2008, Version 0.0)
14
AMIC Technology Corp.
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