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A25L020-U

(A25L010 - A25L512) Serial Flash Memory

AMIC Technology 

SPI MODES

These devices can be driven by a microcontroller with its SPI

peripheral running in either of the two following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising

edge of Serial Clock (C), and output data is available from the

A25L016 Series

falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 2,

is the clock polarity when the bus master is in Stand-by mode

and not transferring data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

Figure 1. Bus Master and Memory Devices on the SPI Bus

SPI Interface with

(CPOL, CPHA)

= (0, 0) or (1, 1)

SDO

SDI

SCK

Bus Master

(ST6, ST7, ST9,

ST10, Other)

CS3 CS2 CS1

C DO DIO

SPI Memory

Device

S W HOLD

C DO DIO

SPI Memory

Device

S W HOLD

C DO DIO

SPI Memory

Device

S W HOLD

Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.

Figure 2. SPI Modes Supported

CPOL CPHA

0

0

C

1

1

C

DIO

DO

MSB

MSB

(April, 2008, Version 0.0)

4

AMIC Technology Corp.

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