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A29DL322UV-70

32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

AMIC Technology 

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7.

Table 13 and the following subsections describe the function

of these bits. I/O7 and I/O6 each offer a method for

determining whether a program or erase operation is

complete or in progress. The device also provides a

hardware-based output signal, RY/BY , to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

I/O7: Data Polling

The Data Polling bit, I/O7, indicates to the host system

whether an Embedded Algorithm is in progress or completed,

or whether the device is in Erase Suspend. Data Polling is

valid after the rising edge of the final WE pulse in the

program or erase command sequence.

During the Embedded Program algorithm, the device outputs

on I/O7 the complement of the datum programmed to I/O7.

This I/O7 status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to I/O7.

The system must provide the program address to read valid

status information on I/O7. If a program address falls within a

protected sector, Data Polling on I/O7 is active for

approximately 1µs, then the device returns to reading array

data.

During the Embedded Erase algorithm, Data Polling

produces a "0" on I/O7. When the Embedded Erase algorithm

is complete, or if the device enters the Erase Suspend mode,

Data Polling produces a "1" on I/O7. The system must

provide an address within any of the sectors selected for

erasure to read valid status information on I/O7.

After an erase command sequence is written, if all sectors

selected for erasing are protected, Data Polling on I/O7 is

active for approximately 100µs, then the bank returns to

reading array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are protected.

However, if the system reads I/O7 at an address within a

protected sector, the status may not be valid.

Just prior to the completion of an Embedded Program or

Erase operation, I/O7 may change asynchronously with I/O0–

I/O6 while Output Enable ( OE ) is asserted low. That is, the

device may change from providing status information to valid

data on I/O7. Depending on when the system samples the

I/O7 output, it may read the status or valid data. Even if the

device has completed the program or erase operation and

I/O7 has valid data, the data outputs on I/O0-I/O6 may be still

invalid. Valid data on I/O0-I/O7 will appear on successive read

cycles.

Table 13 shows the outputs for Data Polling on I/O7. Figure

5 shows the Data Polling algorithm. Figure 19 in the AC

Characteristics section shows the Data Polling timing

diagram.

A29DL32x Series

START

Read I/O7-I/O0

Address = VA

Yes

I/O7 = Data ?

No

No

I/O5 = 1?

Yes

Read I/O7 - I/O0

Address = VA

Yes

I/O7 = Data ?

No

FAIL

PASS

Note :

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. I/O7 should be rechecked even if I/O5 = "1" because

I/O7 may change simultaneously with I/O5.

Figure 5. Data Polling Algorithm

PRELIMINARY (May, 2005, Version 0.0)

26

AMIC Technology, Corp.

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