A29L004AUL-70F Ver la hoja de datos (PDF) - AMIC Technology
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A29L004AUL-70F Datasheet PDF : 39 Pages
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Timing Waveforms for Alternate CE Controlled Write Operation
A29L004A Series
Addresses
WE
OE
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
tWC
tAS
tWH
tAH
Data Polling
PA
tCP
tWHWH1 or 2
CE
tWS
tCPH
tDS
tDH
tBUSY
Data
I/O7
tRH
A0 for program
PD for program
30 for sector erase 10
55 for erase
for chip erase
RESET
RY/BY
DOUT
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time (Note 3)
Typ. (Note 1)
1
11
17
6
Max. (Note 2)
8
64
200
13.5
Unit
Comments
sec Excludes 00h programming
sec prior to erasure
µs
Excludes system-level
sec overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.
PRELIMINARY (March, 2005, Version 0.0)
29
AMIC Technology, Corp.
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