A43L0632G-6F Ver la hoja de datos (PDF) - AMIC Technology

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Lista de partido

A43L0632G-6F

512K X 32 Bit X 2 Banks Synchronous DRAM

AMIC Technology 

Page Read & Write Cycle at Same Bank @Burst Length=4

A43L0632

0

CLOCK

CKE

CS

RAS

CAS

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

High

tRCD

*Note 2

ADDR

Ra

Ca0

Cb0

Cc0

Cd0

BA

A10/AP

Ra

WE

DQM

*Note 2

*Note1

tCDL

tRDL

*Note3

DQ

(CL=2)

Qa0 Qa1 Qb0 Qb1

Dc0 Dc1 Dd0 Dd1

DQ

(CL=3)

Qa0 Qa1 Qb0

Dc0 Dc1 Dd0 Dd1

Row Active

(A-Bank)

Read

(A-Bank)

Read

(A-Bank)

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus

contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input

data after Row precharge cycle will be masked internally.

PRELIMINARY (February, 2007, Version 0.1)

25

AMIC Technology, Corp.

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