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A45L9332AF-6

256K X 32 Bit X 2 Banks Synchronous Graphic RAM

AMIC Technology 

A45L9332A Series

Simplified Truth Table

4. A10 : Bank select address.

If “Low” at read, (block) write, Row active and precharge, bank A is selected.

If “High” at read, (block) write, Row active and precharge, bank B is selected.

If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.

5. It is determined at Row active cycle.

whether Normal/Block write operates in write per bit mode or not.

For A bank write, at A bank Row active, for B bank write, at B bank Row active.

Terminology : Write per bit = I/O mask

(Block) Write with write per bit mode = Masked (Block ) Write

6. During burst read or write with auto precharge, new read/ (block) write command cannot be issued.

Another bank read/(block) write command can be issued at tPR after the end of burst.

7. Burst stop command is valid only t full page burst length.

8. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

9. Graphic features added to SDRAM’s original features.

If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ’s.

SGRAM vs SDRAM

Function

DSF

SGRAM

Function

MRS

L

H

MRS

SMRS

Bank Active

L

H

Bank Active

Bank Active

with

with

Write per bit Write per bit

Disable

Enable

IF DSF is low, SGRAM functionality is identical to SDRAM functionality.

SGRAM can be used as an unified memory by the appropriate DSF control

→SDRAM = Graphic Memory + main Memory

Write

L

H

Normal

Write

Block

Write

PRELIMINARY (October, 2001, Version 0.1)

11

AMIC Technology, Inc.

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