A45L9332A Series
Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
0
CLOCK
CKE
tCH
1
2
3
4
5
tCL
tCC
CS
RAS
tSH
tSS
*Note 1
tRCD
CAS
ADDR
tSH
Ra
tSS
tSH
tSS
Ca
*Note 2
A10
BS
*Note 2,3
BS
6
7
8
9
10 11 12 13 14 15 16 17 18 19
High
tRAS
tRC
tSH
tSS
tRP
tCCD
tSS
Cb
tSH
*Note 2,3
BS
Cc
*Note 2,3 *Note 4
BS BS
Rb
*Note 2
BS
A9
Ra
*Note 3
*Note 3
*Note 3 *Note 4
Rb
WE
DSF
*Note 5
DQM
DQ
tSS
tSH
tSH
tSS
*Note 6
*Note 3
tSS
tSH
tRAC
tSAC
tSLZ
Qa
tOH
tSS
tSHZ
tSH
Db
*Note 5
Qc
Row Active
(Write per Bit
Enable or
Disable)
Read
Write
or
Block Write
Read
Precharge
Row Active
(Write per Bit
Enable or
Disable
: Don't care
PRELIMINARY (October, 2001, Version 0.1)
29
AMIC Technology, Inc.