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A49LF040TX-33F

4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory

AMIC Technology 

A49LF040

Table 14: Pin Impedance (VDD=3.3V, Ta=25°C, f=1MHz, other pins open)

Parameter

Description

Test Condition

Max

CI/O (1)

CIN (1)

LPIN (2)

I/O Pin Capacitance

Input Capacitance

Pin Inductance

VI/O = 0V

VIN = 0V

12pF

12pF

20nH

Notes:

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

2. Refer to PCI specifications.

Table 15: Clock Timing Parameters

Symbol

Parameter

TCYC

THIGH

TLOW

LCLK Cycle Time

LCLK High Time

LCLK Low Time

LCLK Slew Rate (peak-to-peak)

Min

Max

Units

30

ns

11

ns

11

ns

1

4

V/ns

Figure 4: LCLK Waveform

0.5 VDD

0.4 VDD

0.3 VDD

THIGH

0.6 VDD

TCYC

TLOW

0.2 VDD

0.4 VDD Peak-to-Peak

(Min)

Table 16: LPC Mode Read/Write Cycle Timing Parameters, VDD=3.0-3.6V

Symbol

Parameter

Min

TSU

Input Set Up Time to LCLK Rising

7

TDH

LCLK Rising to Data Hold Time

0

TVAL

LCLK Rising to Data Valid

2

TON

LCLK Rising to Active (Float to Active Delay)

2

TOFF

LCLK Rising to Inactive (Active to Float Delay)

Max

Units

ns

ns

11

ns

ns

28

ns

PRELIMINARY (August, 2004, Version 0.1)

15

AMIC Technology, Corp.

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