Figure 10: A/A Mux Mode Read Cycle Timing Diagram
TRSTP
RST#
Address
TRST
Row Address
TAS
TAH
TRC
Column Address
TAS
TAH
R/C#
WE#
VIH
TAA
OE#
High-Z
I/O7-I/O0
TOLZ
TOE
A49LF040
Row Address
Column Address
TOHZ
Data Valid
TOH
High-Z
Figure 11: A/A Mux Mode Write Cycle Timing Diagram
TRSTP
RST#
Address
TRST
Row Address
TAS
TAH
Column Address
TAS
TAH
R/C#
OE#
TOES
TCWH
TWP
TOEH
TWPH
WE#
High-Z
I/O7-I/O0
TDS
TDH
Data Valid
PRELIMINARY (August, 2004, Version 0.1)
20
AMIC Technology, Corp.