A49LF040ATX-33 Ver la hoja de datos (PDF) - AMIC Technology

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A49LF040ATX-33

4 Mbit CMOS 3.3Volt-only Low Pin Count Flash Memory

AMIC Technology 

Figure 3: System Memory Map and Device Memory Map for A49LF040A

D Visio.Drawing.6 |

A49LF040A

Block 7

(64K Bytes)

Block 6

(64K Bytes)

Block 5

(64K Bytes)

Block 4

(64K Bytes)

Block 3

(64K Bytes)

Block 2

(64K Bytes)

Block 1

(64K Bytes)

Block 0

(64K Bytes)

Device Memory

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

A49LF040A

Table 11: Software Data Protection Command Definition

Command

Bus

Cycles

1st Cycle(1)

Addr(2) Data

2nd Cycle

Addr Data

3rd Cycle

Addr Data

4th Cycle

Addr Data

5th Cycle

Addr Data

6th Cycle

Addr Data

Block Erase

Chip Erase(3)

6

YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 80H YYYY 5555H AAH YYYY 2AAAH 55H

BA(4)

30H/50H(5)

6

YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 80H YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 10H

Byte Program

4

YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H A0H

PA(6)

PD(6)

Product ID Entry 3

YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H 90H

Product ID Exit(7)

1

XXXX XXXXH F0H

Product ID Exit(7)

3

YYYY 5555H AAH YYYY 2AAAH 55H YYYY 5555H F0H

Notes:

1. LPC Mode uses consecutive Write cycles to complete a command sequence; A/A Mux Mode uses consecutive bus cycles to complete a

command sequence.

2. YYYY = A[31:16]. In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Table 5. In A/A

Mux mode, YYYY can be VIL or VIH, but no other value.

3. Chip erase is available in A/A Mux Mode only.

4. BA: Block Erase Address.

5. Either 30H or 50H are acceptable for Block Erase.

6. PA: Program Byte Address; PD: Byte data to be programmed.

7. Both Product ID Exit commands are equivalent.

PRELIMINARY (March, 2006, Version 0.1)

14

AMIC Technology, Corp.

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