A49LF040ATX-33F Ver la hoja de datos (PDF) - AMIC Technology
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A49LF040ATX-33F Datasheet PDF : 32 Pages
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A49LF040A
Table 3: LPC Write Cycle
Clock
Cycle
Field
Name
Field Contents LAD[3:0]
LAD[3:0]1
Direction
Comments
1
START
0000
IN
LFRAME must be active (low) for the part to respond. Only the last
start field (before LFRAME transitioning high) should be recognized.
CYCTYPE
2
+ DIR
011X
IN
Indicates the type of cycle. Bits 3:2 must be “01b” for memory cycle.
Bit 1 indicates the type of transfer “1” for Write. Bit 0 is reserved.
3-10 ADDRESS
YYYY
Address Phase for Memory Cycle. LPC protocol supports a 32-bit
IN
address phase. YYYY is one nibble of the entire address. Addresses
are transferred most-significant nibble first. See Table 4 for address
bits definition and Table 5 for valid memory address range.
11
DATA
ZZZZ
IN
This field is the least-significant nibble of the data byte.
12
DATA
ZZZZ
IN
This field is the most-significant nibble of the data byte.
13
TAR0
1111
IN
In this clock cycle, the host has driven the bus to all ‘1’s and then
then Float floats the bus. This is the first part of the bus “turnaround cycle.”
14
TAR1
1111(float)
Float
then OUT
The A49LF040A takes control of the bus during this cycle.
15
SYNC
0000
OUT
The A49LF040A outputs the values “0000b”, indicating that it has
received data or a flash command.
16
TAR0
1111
OUT In this clock cycle, the A49LF040A has driven the bus to all ‘1’s and
then Float then floats the bus. This is the first part of the bus “turnaround cycle.”
17
TAR1
1111(float)
Float
then IN
Host resumes control of the bus during this cycle.
1. Field contents are valid on the rising edge of the present clock cycle.
LPC Write Waveforms
LCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
START
CYCTYPE
+ DIR
ADDRESS
DATA
TAR0 TAR1 SYNC TAR0 TAR1
PRELIMINARY (March, 2006, Version 0.1)
7
AMIC Technology, Corp.
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