A49FL004TL-33 Ver la hoja de datos (PDF) - AMIC Technology
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A49FL004TL-33 Datasheet PDF : 36 Pages
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A49FL004
Table 4: LPC Memory Read Cycle Definition
Clock
Cycle
Field
LAD[3:0] Direction
Descriptions
1
START
CYCTYPE
2
+ DIR
3-10
11
12
13
14-15
16
17
ADDR
TAR0
TAR1
SYNC
DATA
TAR0
TAR1
0000
010x
YYYY
1111
1111
(Float)
0000
1111
1111
1111
(Float)
Start of Cycle: “0000b” indicates the start of a LPC memory
IN
cycle. LFRAME must be active low (low) for the part to respond.
Only the last field latched before LFRAME transitions high will be
recognized.
Cycle Type: Indicates the type of a LPC memory read cycle.
IN
CYCTYPE: Bits 3-2 must be “01b” for memory cycle.
DIR: Bit 1 = “0b” indicates the type of cycle for Read. Bit 0 is
reserved.
Address Cycles: This is the 32-bit memory address. The
IN
addressed transfer most-significant nibble first and least-significant
nibble last. (i.e., a31-28 on LAD[3:0] first, and A3-A0 on LAD[3:0]
last).
IN
Then Float
Float
then OUT
Turn-Around cycle 0: The host has driven the bus to all”1”s and
then float the bus.
Turn-Around cycle 1: The A49FL004 takes control of the bus
during this cycle.
OUT
Sync: The device indicates the least-significant nibble of data byte
will be ready in next clock cycle.
OUT
Data Cycles: The 8-bits data transferred with least-significant
nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on
LAD[3:0] first, then I/O7 – I/O4 on LAD[3:0] last).
IN
Turn-Around cycle 0: The host has driven the bus to all “1”s and
then Float then float the bus.
Float Turn-Around cycle 1: The A49FL004 resumes control of the bus
then OUT during this cycle.
Figure 6: LPC Single-Byte Read Waveforms
LCLK
LFRAME
LAD[3:0]
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
START
CYCTYPE +
DIR
ADDRESS
TAR0 TAR1 SYNC
DATA
TAR0 TAR1
PRELIMINARY (September, 2005, Version 0.0)
10
AMIC Technology, Corp.
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