A49FL004TL-33F Ver la hoja de datos (PDF) - AMIC Technology
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A49FL004TL-33F Datasheet PDF : 36 Pages
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A49FL004
Table 5: LPC Memory Write Cycle Definition
Clock
Cycle
1
Field
START
LAD[3:0]
0000
CYCTYPE
2
011x
+ DIR
3-10
ADDR
YYYY
11-12
DATA
YYYY
13
TAR0
1111
14
TAR1
1111
(Float)
15
SYNC
0000
16
TAR0
1111
17
TAR1
1111
(Float)
Figure 7: LPC Write Waveforms
Direction
Descriptions
Start of Cycle: “0000b” to indicate the start of a LPC memory
IN
cycle. LFRAME must be active low (low) for the part to respond.
Only the last field latched before LFRAME transitions high will be
recognized.
Cycle Type: Indicates the type of a LPC memory write cycle.
IN
CYCTYPE: Bits 3-2 must be “01b” for memory cycle.
DIR: Bit 1 = “1b” indicates the type of cycle for Write. Bit 0 is
reserved.
Address Cycles: This is the 32-bit memory address. The
IN
addressed transfer most-significant nibble first and least-significant
nibble last. (i.e., a31-28 on LAD[3:0] first, and A3-A0 on LAD[3:0]
last).
Data Cycles: The 8-bits data transferred with least-significant
IN
nibble first and most-significant nibble last. (i.e., I/O3 – I/O0 on
LAD[3:0] first, then I/O7 – I/O4 on LAD[3:0] last).
IN
then Float
Float
then OUT
Turn-Around cycle 0: The host has driven the bus to all”1”s and
then float the bus.
Turn-Around cycle 1: The A49FL004 takes control of the bus
during this cycle.
OUT
Sync: The device indicates the least-significant nibble of data byte
will be ready in next clock cycle.
OUT Turn-Around cycle 0: The A49FL004 has driven the bus to all “1”s
then Float and then float the bus.
Float Turn-Around cycle 1: The host resumes control of the bus during
then IN this cycle.
LCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
LFRAME
LAD[3:0]
START
CYCTYPE
+ DIR
ADDRESS
DATA
TAR0 TAR1 SYNC TAR0 TAR1
PRELIMINARY (September, 2005, Version 0.0)
11
AMIC Technology, Corp.
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