Figure 15: A/A Mux Mode Write Cycle Timing Diagram
TR STP
RST
Address
TRST
R owA ddress
TAS
TAH
C olumnA ddress
TAS
TAH
R/C
OE
TO ES
TCWH
T WP
T OEH
TWPH
WE
I/ O7 -I /O0
High-Z
TDS
TDH
D ataValid
A49FL004
Figure 16: A/A Mux Mode Data# Polling Timing Diagram
Address
R/C
Row
Address
Column
Address
WE
OE
High-Z
I/O7
Data
In
Final Input Command
Row
Address
Column
Address
Row
Address
Column
Address
TOEP
Data#
Status Bit
Data#
Status Bit
Command Input
Write Operation In
Progress
Figure 17: A/A Mux Mode Toggle Bit Timing Diagram
Address
R/C
Row
Address
Column
Address
WE
OE
High-Z
I/O6
Data
In
Final Input Command
Row
Address
Column
Address
Row
Address
Column
Address
TOET
Status Bit
Status Bit
Command Input
Write Operation In
Progress
Row
Address
Column
Address
Data
Data
Write Operation
Complete
Row
Address
Column
Address
Data
Data
Write Operation
Complete
PRELIMINARY (September, 2005, Version 0.0)
26
AMIC Technology, Corp.