A6173081S Ver la hoja de datos (PDF) - AMIC Technology

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A6173081S

128K X 8 BIT HIGH SPEED CMOS SRAM

AMIC Technology 

Timing Waveforms (continued)

Write Cycle 1(6)

(Write Enable Controlled)

Address

CE

(4)

tAS1

WE

DIN

DOUT

Write Cycle 2

(Chip Enable Controlled)

Address

CE

tAS1

(4)

WE

DIN

DOUT

A6173081 Series

tWC

tAW

tCW 5

tWP2

tWR 3

tDW

tWHZ7

tDH

tOW 7

tWC

tAW

tCW 5

tWP2

tDW

tWHZ7

tWR 3

tDH

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE and a low WE .

3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle

4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs

remain in a high impedance state.

5. tCW is measured from the later of CE going low to the end of Write.

6. OE is continuously low. ( OE = VIL)

7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (July, 2000, Version 0.0)

7

AMIC Technology, Inc.

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