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CS5542-KL

22-Bit, Multi-Channel ∆Σ ADC Chip Set

Cirrus Logic 

CS5542 CS5543

The CS5542 includes two modulators. The input

current into each of the modulators is set by the fol-

lowing factors: the MCLK (modulator clock) fre-

quency, the value of the VREF voltage to

modulator chip, and the logic value of the CAP-

SIZE input to the CS5542 modulator (this selects

either a 1.6 pF or a 4.8 pF transimpedance feedback

capacitor). MCLK is typically set as some frequen-

cy between 1.024 MHz and 2.048 MHz. The

VREF voltage is optimally set to 4.0 Volts. The

voltage reference for the modulator is actually in-

put into both the VREF+ and VREF- pins as +4.0

and -4.0 volts.

The full scale input current is defined by the fol-

lowing equation:

(VREF) X (CDAC) X (MCLK/16) = IFS

With VREF = 4.0, MCLK = 2.048 MHz, and

CDAC set to select 1.6 pF, the nominal full scale

current will be set at 819 nA. The value of the off-

set and gain register contents will affect the actual

conversion words which are output from the con-

verter with a specific input current. Several calibra-

tion steps (to be discussed later) are necessary to

ensure that the chip converts accurately.

The CS5542 dual modulator and CS5543 multi-

channel filter are designed to interface together.

The CS5542 modulator uses a tri-level modulator.

The modulator thresholds must be calibrated before

accurate measurements can be accomplished. The

threshold values are measured and digitally cor-

rected inside the CS5543 digital filter. The

CS5543 digital filter functions as a digital calibra-

tion engine and a communications interface in ad-

dition to being an FIR filter.

The CS5543 digital filter collects the multi-bit

quantized data from four dual modulator CS5542s

and computes offset and gain corrections to the da-

ta, yielding a 24-bit output word. The 24-bit output

data word includes an overflow bit, a parity bit, and

22 data bits (21 bits plus sign).

There are several clocks which control the timing

to the multi-channel system. CLKIN (Master

Clock) is the primary clock to the system. CLKIN

(typically 2.048 MHz) is input to the CS5543 filter.

Inside the filter CLKIN is buffered and passed to

the CS5542s as MCLK. For each two clock cycles

of MCLK to the modulator, a four bit modulator

sample is passed to the CS5543 digital filter. The

digital filter computes an output conversion word

for each set of 1024 modulator samples. The out-

put word rate of the filter is therefore related to the

CLKIN or MCLK frequency by the ratio

CLKIN/2048 = OWR (output word rate). The con-

version data for eight CS5542 modulator channels

is output from the four CS5543 DATAOUT pins in

a serial-formatted, time-multiplexed fashion. The

DATACLK controls the rate at which data is output

from the DATAOUT pins. DATACLK is three

times the frequency of CLKIN.

The CS5542/CS5543 chip set is designed to sup-

port constructing a serially-connected current digi-

tization system with up to 1024 channels.

System Initialization and Calibration

After power is applied to the CS5542/CS5543 sys-

tem, a reset must be issued to the CS5543 device by

taking the RST pin low. This resets the gain regis-

ter to 0.8 (199998(H)) and all other registers to 0.0.

After RST is returned high, the release of the RST

state is not recognized until the next rising edge of

the FRAME signal.

After a reset is recognized, the CS5542/CS5543

system must complete a full set of calibration

steps before being used for measurement. Cali-

brations are performed by controlling the states

of the DTEST (Digital Test Mode Select) pins

with the DATSEL (Data Select Mode) pins held

as logic 0s. Tables 1 and 2 illustrate the com-

mands available via the DTEST and DATSEL

DS109PP2

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