CS5542-KL Ver la hoja de datos (PDF) - Cirrus Logic
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CS5542-KL Datasheet PDF : 30 Pages
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CS5542 CS5543
ANALOG CHARACTERISTICS: (TA = 25° C; VA+, VD+ = 5 V ±5%; VA- = -5 V ±5%; GNDL,GNDR,
& DGND= 0V;VREF+ = 4V, VREF- = -4 V; MCLK frequency as noted.)
Parameter
Min
Typ
Max
Units
Specified Temperature Range
0
Accuracy
Full Scale Input Current (Bipolar)
CAPSIZE=0
CAPSIZE=1
(Note 1)
-
(Note 1)
-
Dynamic Range
CAPSIZE=0
CAPSIZE=1
(Note 1)
106
(Note 1)
113
Differential Nonlinearity (No Missing Codes) (Note 2)
22
Integral Nonlinearity
(Note 1)
-
Full Scale Error
(Note 3)
-
Full Scale Drift
(Note 3)
-
System Offset Calibration Range
(Note 4)
-
Offset Drift
(Note 1)
-
Power Supplies
(Note 5)
Consumption
Active
-
Powerdown
-
50, 60 Hz Power Supply Rejection: VA+ or VA- (Notes 1, 6)
-
Fullscale Current = 400 nA
60 Hz
-
500 Hz
-
Fullscale Current = 2500 nA
60 Hz
-
500 Hz
-
-
70
°C
400
2500
109
116
-
-
-
30
-
±0.3
-
-
-
-
-
0.001
0.1
-
10
-
nA
nA
dB
dB
Bits
%FS
%FS
ppm/°C
%FS
LSB/°C
-
-
TBD
1.85
13.5
1.88
15.3
80
mW
10
mW
-
dB
-
nA/V
-
nA/V
-
nA/V
-
nA/V
Notes: 1. Full scale current is tested under two conditions: CAPSIZE = 0 (CDAC = 1.6 pF) with MCLK at 1.024
MHz and CAPSIZE = 1 (CDAC = 4.8 pF) with MCLK at 2.048 MHz. Dynamic Range (Signal-to-Noise) is
tested with 101 Hz sine wave voltage driven into a 5 MΩ input resistor with a 470 pF capacitor connected
from INR or INL to REFGNDR or REFGNDL respectively, to test each modulator. S/N and integral
nonlinearity are tested with CAPSIZE = 0 (CDAC = 1.6 pF) with MCLK at 2.048 MHz and CAPSIZE = 1
(CDAC = 4.8 pF) with MCLK at 1.024 MHz.
2. Guaranteed by design or characterization.
3. Specification applies after a complete calibration sequence using the CS5542/CS5543 combination. Drift
specification is for the CS5542/CS5543 only and does not include drift due to the input components, the
VREF voltage, or a frequency change of CLKIN.
4. Specification applies only to System Offset Calibration using the CS5542/CS5543 chip combination after
Input Offset Voltage calibration has been completed with no external offset applied to the input.
5. The VA+ and VA- supplies should be quiet supplies (see data sheet text). Power supply sequence is
important. The VA+ and VA- supplies should be applied to the CS5542 prior to or at the same time as
the VD+ supply.
6. Power supply rejection is tested with a 100 mVp-p sine wave applied to each supply. See data sheet
text for power supply noise requirements.
2
DS109PP2
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