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A8515

Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver

Allegro MicroSystems 

A8515

Wide Input Voltage Range, High Efficiency

Fault Tolerant LED Driver

Functional Description

The A8515 incorporates a current-mode boost controller with

internal DMOS switch, and two LED current sinks. It can be

used to drive two LED strings of up to 12 white LEDs in series,

with current up to 120 mA per string. For optimal efficiency, the

output of the boost stage is adaptively adjusted to the minimum

voltage required by both LED strings. This is expressed by the

following equation:

VOUT = max ( VLED1 , VLED2 ) + VREG

(1)

where

VLEDx is the voltage drop across LED string 1 and 2, and

VREG is the regulation voltage of the LED current sinks (typi-

cally 0.72 V at the maximum LED current).

Enabling the IC

The IC turns on when a logic high signal is applied on the

EN/PWM pin with a minimum duration of tPWMH for the first

clock cycle, and the input voltage present on the VIN pin is

greater than the 4.35 V necessary to clear the UVLO (VUVLOrise )

threshold. The power-up sequence is shown in figure 2. Before

the LEDs are enabled, the A8515 driver goes through a system

check to determine if there are any possible fault conditions that

might prevent the system from functioning correctly. Also, if the

FSET pin is pulled low, the IC will not power-up. More informa-

tion on the FSET pin can be found in the Sync section of this

datasheet.

Powering up: LED pin short-to-GND check

The VIN pin has a UVLO function that prevents the A8515 from

powering-up until the UVLO threshold is reached. After the

VIN pin goes above UVLO, and a high signal is present on the

EN/PWM pin, the IC proceeds to power-up. As shown in figure

3, at this point the A8515 enables the disconnect switch and

checks if any LED pins are shorted to GND and/or are not used.

If an LEDx pin is shorted to ground the A8515 will not proceed

with soft start until the short is removed from the LEDx pin. This

prevents the A8515 from powering-up and putting an uncon-

trolled amount of current through the LEDs. The various detect

scenarios are presented on the next page, in figures 4A to 4C.

The LED detect phase starts when the GATE voltage of the

disconnect switch is equal to VIN – 4.5 V. After the voltage

threshold on the LEDx pins exceeds 120 mV, a delay of between

3000 and 4000 clock cycles is used to determine the status of the

pins. Thus, the LED detection duration varies with the switching

frequency, as shown in the following table:

Switching Frequency

(MHz)

2

1

0.800

0.600

Detection Time

(ms)

1.5 to 2

3 to 4

3.75 to 5

5 to 6.7

VDD

C1

FSET

C2

ISET

C3

EN/PWM

C4

GATE

GATE = VIN – 4.5 V

C1

LEDx

C2

LED detection period

ISET

C3

C4

EN/PWM

t

Figure 2. Power-up diagram; shows VDD (ch1, 2 V/div.), FSET (ch2,

1 V/div.), ISET (ch3, 1 V/div.), and EN/PWM (ch4, 2 V/div.) pins, 200 μs/div.

t

Figure 3. Power-up diagram; shows the relationship of an LEDx pin with

respect to the gate voltage of the disconnect switch (if used) during the

LED detect phase, as well as the duration of the LED detect phase for a

switching frequency of 2 MHz; shows GATE (ch1, 5 V/div.), ILED (ch2,

500 mV/div.), ISET (ch3, 1 V/div.), and EN/PWM (ch4, 5 V/div.) pins,

500 μs/div.

Allegro MicroSystems, Inc.

11

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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