GS88218BD-133I Ver la hoja de datos (PDF) - Giga Semiconductor
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GS88218BD-133I Datasheet PDF : 33 Pages
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GS88218/36BB/D-250/225/200/166/150/133
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
L
LBO
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ
H
Active
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
L
SCD
H or NC
Dual Cycle Deselect
Single Cycle Deselect
Note:
There are pull-up devices on the SCD and FT pins and a pull-down devices on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16, x32, or x64) mode.
Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 1.00b 12/2002
9/33
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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