5962-9458501H4X Ver la hoja de datos (PDF) - Aeroflex Corporation
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5962-9458501H4X Datasheet PDF : 12 Pages
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Device Operation
The ACT-E128K32 is a high-performance
Electrically Erasable and Programmable
Read Only Memory. It is composed of four 1
megabit memory chips and is organized as
131,072 by 32 bits. The device offers access
times of 120 to 300ns with power dissipation
of 1.375W. When the device is deselected,
the CMOS standby current is less than 5 mA.
The ACT-E128K32 is accessed like a Static
consists of setting the WE line low. The write
cycle begins when the last of either CE or
WE goes low.
The WE line transition from high to low also
initiates an internal delay timer to permit
page mode operation. Each subsequent WE
transition from high to low that occurs before
the completion of the tBLC time out will restart
the timer from zero. The operation of the
timer is the same as a retriggable one-shot.
RAM for the read or write cycle without the
need for external components. The device READ
contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously.
During a write cycle, the address and 1 to
128 bytes of data are internally latched,
freeing the address and data bus for other
operations. Following the initiation of a write
cycle, the device will automatically write the
latched data using an internal control timer.
The ACT-E128K32 stores data at the
memory location determined by the address
pins. When CE and OE are low and WE is
high, this data is present on the outputs.
When CE and OE are high, the outputs are in
a high impedance state. This two line control
prevents bus contention.
A
The end of a write cycle can be detected by
DATA polling of I/O7. Once the end of a write
cycle has been detected a new access for a
read or write can begin.
Aeroflex’s ACT-E128K32 has additional
features to ensure high quality and
manufacturability. The device utilizes internal
error correction for extended endurance and
improved data retention characteristics. An
optional software data protection mechanism
is available to guard against inadvertent
writes.
DATA POLLING
The ACT-E128K32 offers a data polling
feature which allows a faster method of
writing to the device. Figure 5 shows the
timing diagram for this function. During a
byte or page write cycle, an attempted read
of the last byte written will result in the
complement of the written data on I/O7 (For
each Chip). Once the write cycle has been
completed, true data is valid on all outputs
and the next cycle may begin. Data polling
may begin at any time during the write cycle.
WRITE
A write cycle is initiated when OE is high and PAGE WRITE OPERATION
a low pulse is on WE or CE with CE or WE
low. The address is latched on the falling
edge of CE or WE whichever occurs last.
The data is latched by the rising edge of CE
or WE, whichever occurs first. A byte write
operation will automatically continue to
completion.
The ACT-E128K32 has a page write
operation that allows one to 128 bytes of data
to be written into the device and
consecutively loads during the internal
programming period. Successive bytes may
be loaded in the same manner after the first
data byte has been loaded. An internal timer
begins a time out operation at each write
WRITE CYCLE TIMING
Figures 2 and 3 show the write cycle timing
relationships. A write cycle begins with
address application, write enable and chip
enable. Chip enable is accomplished by
placing the CE line low. Write enable
cycle. If another write cycle is completed
within tBLC or less, a new time out period
begins. Each write cycle restarts the delay
period. The write cycles can be continued as
long as the interval is less than the time out
period.
Aeroflex Circuit Technology
4
SCD1662 REV B 9/5/01 Plainview NY (516) 694-6700
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