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ACT5830QJ1CF-T Ver la hoja de datos (PDF) - Active-Semi, Inc

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ACT5830QJ1CF-T
ACTIVE-SEMI
Active-Semi, Inc ACTIVE-SEMI
ACT5830QJ1CF-T Datasheet PDF : 41 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
®
ACT5830
Rev 2, 20-Jan-11
SYSTEM MANAGEMENT
I2C INTERFACE ELECTRICAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
SCL, SDA Low Input Voltage
SCL, SDA High Input Voltage
SCL, SDA Leakage Current
SDA Low Output Voltage
SCL Clock Period, tSCL
SDA Data In Setup Time to SCL High, tSU
SDA Data Out Hold Time after SCL Low, tHD
SDA Data Low Setup Time to SCL Low, tST
SDA Data High Hold Time after Clock High, tSP
VCHG_IN = 4.2V
IOL = 5mA
fSCL clock freq = 400kHz
Start Condition
Stop Condition
MIN TYP MAX UNIT
0.4
V
1.4
V
1
µA
0.3
V
2.5
µs
100
ns
300
ns
100
ns
100
ns
Figure 1:
I2C Serial Bus Timing
Note: Each session of data transfer is with a start condition, a 7-bits slave address plus a bit to instruct for read or write followed by an
acknowledge bit, a register address byte followed by an acknowledge bit, a data byte followed by an acknowledge bit and a stop condi-
tion. The device address, the register address and the data are all MSB first transferred. Each bit volume is prepared in during the SCL
is low, is latched-in by the rising edge of the SCL. The data byte is accepted and is put effective by the time that the last bit volume is
latched-in.
Innovative PowerTM
-9-
ActivePMUTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP.
www.active-semi.com
Copyright © 2010 Active-Semi, Inc.

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