AD1836 Ver la hoja de datos (PDF) - Analog Devices
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AD1836 Datasheet PDF : 18 Pages
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PRELIMINARY TECHNICAL DATA
AD1836
The word width defaults to 24 bits but can be changed by
reprogramming Bits 3 and 4 in DAC Control Register 1. The
packed modes accept six channels of data at the DSDATA1
input pin which is independently routed to each of the six
internal DACs.
A special “auxiliary mode” is provided to allow two external
stereo ADCs and one external stereo DAC to be interfaced to
the AD1836 to provide 8-in/8-out operation. In addition, this
mode supports glueless interface to a single SHARC DSP serial
port, allowing a SHARC DSP to access all eight channels of
analog I/O. In this special mode, many pins are redefined; see
Table I for a list of redefined pins. Two versions of this mode
are available. In the “master” mode, the AD1836 provides the
LRCLK and BCLK signals, and the external ADCs operate in
slave mode. In the “slave” mode, the external ADCs provide the
LRCLK and BCLK signals (which must be divided down prop-
erly from the external master clock), and the AD1836 will sync
to these external clocks. See Figures 8 through 10 for details of
this mode. Figure 11 shows the internal signal-flow diagram of
the auxiliary mode.
The following figures show the serial mode formats.
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LEFT-JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
12S MODE – 16 TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE – 16 TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 ؋ fS
3. BCLK FREQUENCY IS NORMALLY 64 ؋ LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 3. Stereo Serial Modes
–10–
REV. PrC
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