AD1838A Ver la hoja de datos (PDF) - Analog Devices
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AD1838A Datasheet PDF : 24 Pages
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AD1838A
TIMING SPECIFICATIONS
Parameter
MASTER CLOCK AND RESET
tMH
MCLK High
tML
MCLK Low
tPDR
PD/RST Low
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCOE
tCOD
tCOTS
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
tDBH
DBCLK High
tDBL
DBCLK Low
fDB
DBCLK Frequency
tDLS
DLRCLK Setup
tDLH
DLRCLK Hold
tDDS
DSDATA Setup
tDDH
DSDATA Hold
Packed 128/256 Modes (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
tABD
ABCLK Delay
tALD
ALRCLK Delay
tABDD
ASDATA Delay
Normal Mode (Slave)
tABH
ABCLK High
tABL
ABCLK Low
fAB
ABCLK Frequency
tALS
ALRCLK Setup
tALH
ALRCLK Hold
tABDD
ASDATA Delay
Packed 128/256 Mode (Master)
tPABD
tPALD
tPABDD
ABCLK Delay
LRCLK Delay
ASDATA Delay
Min
Max
15
15
20
40
40
80
10
10
10
10
15
20
25
60
60
64 ϫ fS
10
10
10
10
15
15
256 ϫ fS
10
10
10
10
25
5
10
60
60
64 ϫ fS
5
15
15
40
5
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
To CCLK Rising Edge
From CCLK Rising Edge
To CCLK Rising Edge
From CCLK Rising Edge
From CLATCH Falling Edge
From CCLK Falling Edge
From CLATCH Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
To ABCLK Rising Edge
From ABCLK Rising Edge
From ABCLK Falling Edge
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
–4–
REV. A
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