AD1935 Ver la hoja de datos (PDF) - Analog Devices
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AD1935 Datasheet PDF : 30 Pages
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Preliminary Technical Data
Parameter
I2C PORT
Start Condition
Stop Condition
Slave Mode
DAC SERIAL PORT
Master Mode
Slave Mode
ADC SERIAL PORT
Master Mode
AUXILIARY INTERFACE
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLH
tCOE
tCOD
tCOH
tCOTS
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tSCS
tDBH
tDBL
fDB
tDLS
tDLH
tDLS
tDDS
tDDH
tABH
tABL
fDB
tALS
tALH
tALS
tABDD
tAXDS
tAXDH
tDXDD
tXBH
tXBL
fXB
tDLS
tDLH
AD1935/AD1936/AD1937/AD1938/AD1939
CCLK Frequency
CDATA Setup
CDATA Hold
CLATCH Setup
Comments
To CCLK Rising
From CCLK Rising
To CCLK Rising
CLATCH Hold
From CCLK Falling
CLATCH High
COUT Enable
From CCLK Falling
COUT Delay
COUT Hold
COUT Three-State
SCL Clock
Frequency
SCL High
SCL Low
Setup Time
Hold Time
Data Setup Time
SCL Rise Time
From CCLK Falling
From CCLK Falling
From CCLK Falling
Relevant for Repeated Start
Condition
After this period the 1st clock is
generated
SCL Fall Time
SDA Rise Time
SDA Fall Time
Setup Time
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DLRCLK Skew
DSDATA Setup
DSDATA Hold
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
To DBCLK Rising
From DBCLK Rising
From DBCLK Falling
To DBCLK Rising
From DBCLK Rising
To ABCLK Rising
From ABCLK Rising
ALRCLK Skew
ASDATA Delay
AAUXDATA Setup
AAUXDATA Hold
DAUXDATA Delay
AUXBCLK High
AUXBCLK Low
AUXBCLK
Frequency
AUXLRCLK Setup
AUXLRCLK Hold
From ABCLK Falling
From ABCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
From AUXBCLK Falling
To AUXBCLK Rising
From AUXBCLK Rising
Table 8
Min Max Unit
20
MHz
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
400
kHz
0.6
µS
1.3
µS
0.6
µS
0.6
µS
100
ns
300
ns
300
ns
300
ns
300
ns
0.6
µS
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
TBD
ns
Rev. PrI | Page 5 of 30
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