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AD1939WBSTZ Datasheet PDF : 32 Pages
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AD1939
DIGITAL FILTERS
Table 6.
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
Data Sheet
Mode
All modes, typical @ 48 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
48 kHz mode, typical @ 48 kHz
96 kHz mode, typical @ 96 kHz
192 kHz mode, typical @ 192 kHz
Factor
0.4375 fS
0.5 fS
0.5625 fS
22.9844/fS
0.4535 fS
0.3646 fS
0.3646 fS
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
25/fS
11/fS
8/fS
Min Typ
Max
Unit
21
kHz
±0.015
dB
24
kHz
27
kHz
79
dB
479
µs
22
35
70
24
48
96
26
61
122
70
70
70
521
115
42
kHz
kHz
kHz
±0.01 dB
±0.05 dB
±0.1
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
µs
µs
µs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK) AND
RESET
tMH
Condition
MCLK duty cycle
tMH
fMCLK
fMCLK
tPDR
tPDRR
PLL
Lock Time
256 fS VCO Clock, Output Duty Cycle,
MCLKO/XO Pin
MCLK frequency
Low
Recovery
MCLK and LRCLK input
Comments
DAC/ADC clock source = PLL clock @ 256 fS, 384
fS, 512 fS, and 768 fS
DAC/ADC clock source = direct MCLK @ 512 fS
(bypass on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
Reset to active output
Min Max Unit
40 60 %
40 60 %
6.9 13.8 MHz
27.6 MHz
15
ns
4096
tMCLK
10 ms
40 60 %
Rev. E | Page 6 of 32
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