AD5227 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Lista de partido
AD5227 Datasheet PDF : 16 Pages
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AD5227
Parameter
Symbol
INTERFACE TIMING CHARACTERISTICS (applies to all parts6, 10)
Clock Frequency
fCLK
Input Clock Pulse Width
tCH, tCL
CS to CLK Setup Time
tCSS
CS Rise to CLK Hold Time
tCSH
U/D to Clock Fall Setup Time
tUDS
Conditions
Min Typ1 Max
Unit
Clock level high or low 10
10
10
10
50
MHz
ns
ns
ns
ns
1 Typicals represent average readings at 25°C, VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
4 DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9 All dynamic characteristics use VDD = V.
10 All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using
VDD = 5 V.
INTERFACE TIMING DIAGRAMS
CS = LOW
U/D = HIGH
CLK
RWB
CS = LOW
U/D = 0
CLK
Figure 2. Increment RWB
RWB
Figure 3. Decrement RWB
1
CS
0
tCSS
tCH
1
tCL
CLK
0
tUDS
1
U/D
0
tS
RWB
tCSH
Figure 4. Detailed Timing Diagram (Only RWB Decrement Shown)
Rev. B | Page 4 of 16
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