CS4228A(2000) Ver la hoja de datos (PDF) - Cirrus Logic
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CS4228A Datasheet PDF : 32 Pages
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CS4228A
SWITCHING CHARACTERISTICS (Continued)
Parameter
Symbol Min
Typ
RST Low Time
(Note 9)
1
-
SCLK Falling Edge to SDOUT Output Valid
(DSCK=0) tdpd
-
LRCK Edge to MSB Valid
tlrpd
-
SDIN Setup Time Before SCLK Rising Edge
tds
-
SDIN Hold Time After SCLK Rising Edge
tdh
-
Master Mode
SCLK Falling to LRCK Edge
SCLK Duty Cycle
tmslr
+10
50
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK Edge
LRCK Edge to SCLK Rising
tsckw
-
tsckh
50
-
tsckl
50
-
(DSCK=0) tlrckd
25
-
(DSCK=0) tlrcks
25
-
Max
-
50
20
10
30
Units
ms
ns
ns
ns
ns
-
ns
-
%
-
ns
-
ns
-
ns
-
ns
-
ns
Notes: 9. After powering up the CS4228A, RST should be held low until the power supplies and clocks are settled.
SCLK*
(output)
LRCK
(output)
SDOUT
t mslr
Figure 1. Serial Audio Port Master Mode Timing
LRCK
(input)
t lrckd
t lrcks
t sckh
tsckl
SCLK*
(input)
SDIN1
SDIN2
SDIN3
SDOUT
t sckw
tlrpd tds
tdh
MSB
tdpd
MSB-1
*SCLK shown for DSCK = 0.
SCLK inverted for DSCK = 1.
Figure 2. Serial Audio Port Slave Mode Timing
DS511PP1
7
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