CS4228A-KS(2000) Ver la hoja de datos (PDF) - Cirrus Logic
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CS4228A-KS Datasheet PDF : 32 Pages
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CS4228A
SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25° C; VA = VD = +5 V,
VL=2.375 to 5.25 V; Inputs: logic 0 = DGND, logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
Max
Units
Two Wire Mode (SDOUT < 47 kΩ to ground)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
fscl
-
100
kHz
tbuf
4.7
µs
thdst
4.0
µs
Clock Low Time
Clock High Time
tlow
4.7
µs
thigh
4.0
µs
Setup Time for Repeated Start Condition
tsust
4.7
µs
SDA Hold Time from SCL Falling
(Note 12)
thdd
0
µs
SDA Setup Time to SCL Rising
tsud
250
ns
Rise Time of Both SDA and SCL Lines
tr
1
µs
Fall Time of Both SDA and SCL Lines
tf
300
ns
Setup Time for Stop Condition
tsusp
4.7
µs
Notes: 12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop Start
Repeated
Start
SDA
SCL
t buf
t hdst
t high
t hdst
tf
t low t hdd
t sud
t sust
tr
Figure 4. Two Wire Control Port Timing
Stop
t susp
DS511PP1
9
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