LS7166-TS24(2002) Ver la hoja de datos (PDF) - LSI Corporation
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LS7166-TS24 Datasheet PDF : 12 Pages
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TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig. 7,
VDD = 4.5V to 5.5V, TA = 0˚ to 70˚C, unless otherwise specified)
Parameter
Clock A/B "Low”
Clock A/B "High"
Clock A/B Frequency
(See NOTE 1)
Clock UP/DN Reversal
Delay
LCTR Positive edge to
the next A/B positive or
negative edge delay
Clock A/B to
CY/BW/COMP "low"
propagation delay
Clock A/B to
CY/BW/COMP "high"
propagation delay
LCTR and LLTC pulse
width
Clock A/B to CYT, BWT
and COMPT "high"
propagation delay
Clock A/B to CYT, BWT
and COMPT "low"
progagation delay
WR pulse width
RD to data out delay
(CL = 20pF)
CS, RD Terminate to
Data-Bus Tri-State
Symbol
TCL
TCH
fc
TUDD
TLC
TCBL
TCBH
TLCW
TTFH
TTFL
TWW
TR
TRT
Min.Value
20
30
0
100
100
-
-
60
-
-
60
-
-
Max.Value
No Limit
No Limit
20
-
-
65
85
-
100
100
-
110
30
Unit
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data-Bus set-up
time for WR
Data-Bus hold time for WR
C/D, CS set-up time for RD
C/D, CS hold time for RD
C/D set-up time for WR
C/D hold time for WR
CS set-up time for WR
CS holdtime for WR
TDS
TDH
TCRS
TCRH
TCWS
TCWH
TSWS
TSWH
15
-
30
-
0
-
0
-
15
-
30
-
15
-
0
-
ns (see Note 3)
ns (see Note 3)
ns
ns
ns (see Note 3)
ns (see Note 3)
ns (see Note 3)
ns (see Note 3)
Quadrature Mode:
Clock A/B Validation delay
(See NOTE 2)
A and B phase delay
Clock A/B frequency
CY, BW, COMP pulse width
TCQV
TPH
fCQ
TCBW
-
160
208
-
-
1.2
75
180
ns
ns
MHz
ns
NOTE 1: A) In Divide by N mode, the maximum clock frequency is 10 MHz.
B) The maximum frequency for valid CY, BW, CYT, BWT, COMP, COMPT is 10 MHz.
NOTE 2: In quadrature mode A/B inputs are filtered and required to be stable
for at least TCQV length to be valid.
NOTE 3: All WR specifications are critical for proper operation of LS7166
7166-120902-6
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