AD6650BBC(2003) Ver la hoja de datos (PDF) - Analog Devices
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AD6650BBC Datasheet PDF : 28 Pages
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Preliminary Technical Data
GENERAL TIMING CHARACTERISTICS
Test
Parameter (Conditions)
Temp Level Min
CLK Timing Requirements:
tCLK
CLK Period
tCLKL
CLK Width Low
tCLKH
CLK Width High
/RESET Timing Requirements:
Full
I
9.6
Full IV
Full IV
tRESL
/RESET Width Low
SYNC Timing Requirements:
Full IV
30
tSS
SYNC to ↑CLK Setup Time
tHS
SYNC to ↑CLK Hold Time
Full IV
Full IV
Master Mode Serial Port Timing Requirements (SBM=1):
Switching Characteristics2
tDSCLK1
tDSCLKH
tDSCLKL
tDSCLKLL
↑CLK to ↑SCLK Delay (divide by 1)
Full IV
3.9
↑CLK to ↑SCLK Delay (for any other divisor) Full IV
4.4
↑CLK to ↓SCLK Delay (divide by 2 or even #) Full
IV
3.25
↓CLK to ↓SCLK Delay (divide by 3 or odd #) Full IV
3.8
tDSDFS
tDSDO
tDSD1
tDSDR
↑SCLK to SDFS Delay
↑SCLK to SDO Delay
↑SCLK to SD1 Delay
↑SCLK to DR Delay
Full IV
Full IV
Full IV
Full IV
Slave Mode Serial Port Timing Requirements (SBM=0):
Switching Characteristics2
tSCLK
tSCLKL
tSCLKH
tDSDO
tDSD1
t DSDR
SCLK Period
Full IV 16.0
SCLK low time (when SDIV=1, divide by 1)
Full IV
5.0
SCLK high time (when SDIV=1, divide by 1) Full IV
5.0
↑SCLK to SDO Delay
Full IV
↑SCLK to SD1 Delay
Full IV
↑SCLK to DR Delay
Full IV
Input Characteristics
tSSF
SDFS to ↑SCLK Setup Time
tHSF
SDFS to ↑SCLK Hold Time
Full IV
Full IV
AD6650
Typ
0.5 x tCLK
0.5 x tCLK
3.02
2.7
2.6
2.7
6.8
6.8
6.9
2.6
-1.15
AD6650
Max Units
ns
ns
ns
ns
ns
ns
13.4
ns
14.0
ns
6.7
ns
6.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V.
2The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1). The Slave serial port’s (SCLK)
operating frequency is limited to 52 MHz.
3Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS
4(CLOAD=40pF on all outputs unless otherwise specified)
REV. PrJ 02/27/2003
6
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