AD6650 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Lista de partido
AD6650 Datasheet PDF : 45 Pages
| |||
AD6650
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V.
Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation
Parameter
Symbol Temp Test Level
WRITE TIMING
WR (R/W) to RDY (DTACK) Hold Time1
tHWR
Full
IV
Address/Data to WR (R/W) Setup Time1
tSAM
Full
IV
Address/Data to RDY (DTACK) Hold Time1
tHAM
Full
IV
WR (R/W) to RDY (DTACK) Delay
tDRDY 2
Full
IV
WR (R/W) to RDY (DTACK) High Delay1
tACC
Full
IV
READ TIMING
Address to RD (DS) Setup Time1
tSAM
Full
IV
Address to Data Hold Time1
Data Three-state Delay1
RDY (DTACK) to Data Delay1
tHAM
Full
IV
tZD
Full
V
tDD
Full
IV
RD (DS) to RDY (DTACK) Delay
tDRDY2
Full
IV
RD (DS) to RDY (DTACK) High Delay1
tACC
Full
IV
Min
0.0
0.0
0.0
9.0
4 × tCLK
0.0
0.0
9.0
4 × tCLK
Typ Max
15.0
13 × tCLK
12
0.0
15.0
13 × tCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 Timing is guaranteed by design.
2 Specification pertains to control signals R/W, WR, DS, RD, and CS such that the minimum specification is valid after the last control signal has reached a valid logic level.
Table 6. Microprocessor Port, Mode MNM (MODE = 1)
Parameter
Symbol
WRITE TIMING
DS (RD) to DTACK (RDY) Hold Time
tHDS
R/W (WR) to DTACK (RDY) Hold Time
tHRW
Address/Data to R/W (WR) Setup Time1
tSAM
Address/Data to R/W (WR) Hold Time1
tHAM
DS (RD) to DTACK (RDY) Delay2
tDDTACK
R/W (WR) to DTACK (RDY) Low Delay1
tACC
READ TIMING
DS (RD) to DTACK (RDY) Hold Time
tHDS
Address to DS (RD) Setup Time1
tSAM
Address to Data Hold Time1
tHAM
Data Three-State Delay
tZD
DTACK (RDY) to Data Delay1
tDD
DS (RD) to DTACK (RDY) Delay2
tDDTACK
DS (RD) to DTACK (RDY) Low Delay1
tACC
1 Timing is guaranteed by design.
2 DTACK is an open-drain device and must be pulled up with a 1 kΩ resistor.
Temp Test Level
Full
IV
Full
IV
Full
IV
Full
IV
Full
V
Full
IV
Full
IV
Full
IV
Full
IV
Full
V
Full
IV
Full
V
Full
IV
Min
15.0
15.0
0.0
0.0
4 × tCLK
15.0
0.0
0.0
4 × tCLK
Typ Max
16
13 × tCLK
13
0.0
16
13 × tCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 6 of 44
Share Link: 