CLK+
DECIMATED
INTERLEAVED
CMOS DATA
DECIMATED
INTERLEAVED
FD DATA
tPD
CHANNEL A:
DATA
CHANNEL A:
FD BITS
DECIMATED
DCO
CHANNEL B:
DATA
CHANNEL B:
FD BITS
CHANNEL A:
DATA
CHANNEL A:
FD BITS
tS
tH
CHANNEL B:
DATA
CHANNEL B:
FD BITS
tDCO
CHANNEL A:
DATA
CHANNEL A:
FD BITS
CHANNEL B:
DATA
CHANNEL B:
FD BITS
Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing
AD6653
CLK+
DECIMATED
CMOS IQ
OUTPUT DATA
CMOS FD
DATA
DECIMATED
DCOA/DCOB
tPD
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
tDCO
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
tS
tH
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing
CHANNEL A/B:
FD BITS
CLK–
CLK+
LVDS
DATA
LVDS
FAST DET
DCO–
DCO+
tPD
CHANNEL A:
DATA
CHANNEL A:
FD
CHANNEL B:
DATA
CHANNEL B:
FD
CHANNEL A:
DATA
CHANNEL A:
FD
tDCO
CHANNEL B:
DATA
CHANNEL B:
FD
CHANNEL A:
DATA
CHANNEL A:
FD
Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing
CLK+
SYNC
tSSYNC
tHSYNC
Figure 7. SYNC Timing Inputs
Rev. 0 | Page 11 of 80