CS4360-DZZ(2004) Ver la hoja de datos (PDF) - Cirrus Logic
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CS4360-DZZ Datasheet PDF : 37 Pages
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CS4360
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE
Inputs: Logic 0 = GND, Logic 1 = VLC
Parameter
Symbol
Min
I²C Mode
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 7)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL and SDA
trc, trc
-
Fall Time SCL and SDA
tfc, tfc
-
Setup Time for Stop Condition
tsusp
4.7
Acknowledge Delay from SCL Falling
(Note 8)
tack
-
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
(Note 9)
ns
Notes: 7. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
8. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
9. ----------5---------- for Single-Speed Mode, ----------5---------- for Double-Speed Mode, --------5--------- for Quad-Speed Mode.
256 × Fs
128 × Fs
64 × Fs
RST
t irs
S to p
S ta rt
SDA
SCL
t buf
t hdst
t high
t
lo w
t
hdd
t sud t ack
R e pe ate d
S ta rt t rd
t hdst
S to p
t fd
t fc
t susp
t sust
t rc
Figure 13. Control Port Timing - I²C Mode
DS517F2
17
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