CS4360-KS Ver la hoja de datos (PDF) - Cirrus Logic

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CS4360-KS

24-Bit, 192 kHz 6 Channel D/A Converter

Cirrus Logic 

CS4360

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT

(Note 16) (For -KS & -KZ parts TA = -10 to +70°C; for -BS & -BZ parts TA = -40 to +85°C; VLC = 1.7 V - 5.5 V;

Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

-

100

kHz

RST Rising Edge to Start

tirs

500

-

ns

Bus Free Time Between Transmissions

tbuf

4.7

-

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

-

µs

Clock Low time

tlow

4.7

-

µs

Clock High Time

thigh

4.0

-

µs

Setup Time for Repeated Start Condition

tsust

4.7

-

µs

SDA Hold Time from SCL Falling

(Note 17) thdd

0

-

µs

SDA Setup time to SCL Rising

tsud

250

-

ns

Rise Time of SCL and SDA

trc, trc

-

1

µs

Fall Time SCL and SDA

tfc, tfc

-

300

ns

Setup Time for Stop Condition

tsusp

4.7

-

µs

Acknowledge Delay from SCL Falling

(Note 18)

tack

-

(Note 19)

ns

Notes: 16. The Two-Wire Format is compatible with the I2C protocol.

17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

19. 2----5---6---5-×-----F----s for Single-Speed Mode, 1----2---8---5-×-----F----s for Double-Speed Mode, 6----4----×5-----F----s for Quad-Speed Mode.

RST

t irs

Stop

Start

SDA

t buf

t hdst

t high

R e p e ate d

Start t rd

t hdst

Stop

t fd

t fc

t susp

SCL

t

low

t

hdd

t sud t ack

t sust

t rc

Figure 2. Control Port Timing - Two-Wire Format

10

DS517PP1

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