AD73322L Ver la hoja de datos (PDF) - Analog Devices
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AD73322L Datasheet PDF : 40 Pages
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AD73322L–SPECIFICATIONS1 (AVDD = 3 V ؎ 10%; DVDD = 3 V ؎ 10%; DGND = AGND = 0 V, fDMCLK =
16.384 MHz, fSAMP = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A, Y Versions
Min Typ Max Unit
Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
INPUT AMPLIFIER
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
ANALOG GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
Total Harmonic Distortion
PGA = 0 dB
Intermodulation Distortion
Idle Channel Noise Crosstalk
ADC-to-DAC
ADC-to-ADC
DC Offset
Power Supply Rejection
Group Delay4, 5
Input Resistance at PGA2, 4, 6
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
1.08 1.2
50
130
1.08 1.2
1
100
1.32 V
ppm/°C 0.1 µF Capacitor Required from
REFCAP to AGND2
Ω
1.32 V
Unloaded
kΩ
pF
± 1.0
1.578
50
100
mV
V
Max Output Swing = (1.578/1.2) × VREFCAP
kΩ
fC = 32 kHz
pF
+1
–1
5
± 1.0
1.0
0.5
1.578
–2.85
1.0954
–6.02
Bits
%
µs
µs
V p-p
dBm
V p-p
dBm
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of –FS to +FS
DAC Unloaded
Measured Differentially
Max Input = (1.578/1.2) × VREFCAP
Measured Differentially
–2.0 –0.7 +0.5 dB
± 0.1
dB
70
78
dB
79
dB
77.5
dB
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to TPC 1.
300 Hz to 3400 Hz; fSAMP = 8 kHz, PUIA = 0
300 Hz to 3400 Hz; fSAMP = 8 kHz, PUIA = 1
0 Hz to fSAMP/2; fSAMP = 8 kHz
–86 –75 dB
–61
dB
300 Hz to 3400 Hz; fSAMP = 8 kHz
PGA = 0 dB
–72
dBm0 PGA = 0 dB
–107
dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
–92
dB
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
–93
dB
Input Amplifiers Included in Input Channel
–20 0
+20 mV
PGA = 0 dB
–65
dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
25
µs
20
kΩ
Input Amplifiers Bypassed
+1
–1
16
Bits Tested to 5 MSBs of Settings
25
µs
Includes DAC Delay
100
µs
Tap Gain Change from –FS to +FS; Includes
DAC Settling Time
–2–
REV. 0
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