EVAL-AD7401AEDZ Ver la hoja de datos (PDF) - Analog Devices

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EVAL-AD7401AEDZ

Isolated Sigma-Delta Modulator

Analog Devices 

AD7401A

Parameter

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL

POWER REQUIREMENTS

VDD1

VDD2

IDD1 5

IDD2 6

Power Dissipation

Y Version1, 2

Min

Typ Max

VDD2 − 0.1

0.4

4.5

5.5

3

5.5

10

12

7

9

3

4

93.5

Unit Test Conditions/Comments

V

IO = −200 μA

V

IO = +200 μA

V

V

mA

VDD1 = 5.5 V

mA

VDD2 = 5.5 V

mA

VDD2 = 3.3 V

mW VDD1 = VDD2 = 5.5 V

1 For fMCLK > 16 MHz to 20 MHz, mark space ratio is 48/52 to 52/48, VDD1 = VDD2 = 5 V ± 5%, and TA = −40°C to +85°C.

2 All voltages are relative to their respective ground.

3 See the Terminology section.

4 Sample tested during initial release to ensure compliance.

5 See Figure 15.

6 See Figure 17.

Rev. 0 | Page 4 of 20

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