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AD7484

3 MSPS, 14-Bit SAR ADC

Analog Devices 

AD7484

Figure 18 shows the AD7484 conversion sequence when the

part is put into nap mode after each conversion.

600ns

1400ns

NAP

CONVST

300ns

BUSY

2µs

Figure 18. Nap Mode Power Dissipation

Figure 19 and Figure 20 show a typical graphical representation

of power vs. throughput for the AD7484 when in normal mode

and nap mode, respectively.

90

85

80

75

70

65

60

0

500

1000

1500

2000

2500

3000

THROUGHPUT (kSPS)

Figure 19. Normal Mode, Power vs. Throughput

90

80

70

60

50

40

30

20

10

0

0

250 500 750 1000 1250 1500 1750 2000

THROUGHPUT (kSPS)

Figure 20. Nap Mode, Power vs. Throughput

In standby mode, all internal circuitry is powered down and the

power consumption of the AD7484 is reduced to 10 µW. The

power-up time necessary before a conversion can be initiated is

longer because more of the internal circuitry has been powered

down. In using the internal reference of the AD7484, the ADC

must be brought out of standby mode 500 ms before a conversion is

initiated. Initiating a conversion before the required power-up time

has elapsed results in incorrect conversion data. If an external

reference source is used and kept powered up while the AD7484 is

in standby mode, the power-up time required is reduced to 80 µs.

OFFSET/OVERRANGE

The AD7484 provides a ±8% overrange capability as well as a

programmable offset register. The overrange capability is achieved

by the use of a 15th bit (D14) and the CLIP input. If the CLIP input

is at logic high and the contents of the offset register are 0, then the

AD7484 operates as a normal 14-bit ADC. If the input voltage is

greater than the full-scale voltage, the data output from the ADC is

all 1s. Similarly, if the input voltage is lower than the zero-scale

voltage, the data output from the ADC is all 0s. In this case, D14

acts as an overrange indicator. It is set to 1 if the analog input

voltage is outside the nominal 0 V to 2.5 V range.

The default contents of the offset register are 0. If the offset reg-

ister contains any value other than 0, the contents of the register

are added to the SAR result at the end of conversion. This has the

effect of shifting the transfer function of the ADC as shown in

Figure 21 and Figure 22. However, it should be noted that with

the CLIP input set to logic high, the maximum and minimum

codes that the AD7484 can output are 0x3FFF and 0x0000,

respectively. Further details are given in Table 5 and Table 6.

Figure 21 shows the effect of writing a positive value to the

offset register. For example, if the contents of the offset register

contained the value 1024, then the value of the analog input

voltage for which the ADC transitions from reading all 0s to

000…001 (the bottom reference point) is

0.5 LSB − (1024 LSB) = −156.326 mV

The analog input voltage for which the ADC reads full-scale

(0x3FFF) in this example is

2.5 – 1.5 LSB – (1024 LSB) = 2.34352 V

111...111

111...110

111...000

011...111

1LSB = VREF/16384

000...010

000...001

000...000

+VREF – 1.5LSB

–OFFSET

ANALOG INPUT

0V

Figure 21. Transfer Characteristic with Positive Offset

The effect of writing a negative value to the offset register is

shown in Figure 22. If a value of −512 is written to the offset

register, the bottom end reference point occurs at

0.5 LSB – (−512 LSB) = 78.20 mW

Following this, the analog input voltage needed to produce a

full-scale (0x3FFF) result from the ADC is

2.5 V – 1.5 LSB – (−512 LSB) = 2.5779 V

Rev. C | Page 14 of 20

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