AD7682 Ver la hoja de datos (PDF) - Analog Devices
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AD7682 Datasheet PDF : 28 Pages
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AD7682/AD7689
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3. 1
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width
Data Write/Read During Conversion
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV Low to SDO D15 MSB Valid
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Falling Edge
DIN Valid Hold Time from SCK Falling Edge
Symbol
Min
Typ
Max
Unit
tCONV
2.2
μs
tACQ
1.8
μs
tCYC
4
μs
tCNVH
10
ns
tDATA
1.4
μs
tSCK
15
ns
tSCKL
7
ns
tSCKH
7
ns
tHSDO
4
ns
tDSDO
16
ns
17
ns
18
ns
19
ns
tEN
15
ns
17
ns
18
ns
22
ns
tDIS
25
ns
tCLSCK
10
ns
tSDIN
4
ns
tHDIN
4
ns
1 See Figure 2 and Figure 3 for load conditions.
Rev. 0 | Page 6 of 28
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