AD7781CRZ-REEL Ver la hoja de datos (PDF) - Analog Devices
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AD7781CRZ-REEL Datasheet PDF : 16 Pages
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AD7781
TIMING CHARACTERISTICS
AVDD = 2.7 V to 5.25 V, DVDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 3.
Parameter1
Read2
t1
t2
t3 3
t4
Reset
t5
t6 5
Limit at TMIN, TMAX
100
100
0
60
80
10
130
100
120
300
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ms typ
ms typ
Test Conditions/Comments
SCLK high pulse width
SCLK low pulse width
SCLK active edge to data valid delay4
DVDD = 4.75 V to 5.25 V
DVDD = 2.7 V to 3.6 V
SCLK inactive edge to DOUT/RDY high
PDRST low pulse width
FILTER/GAIN change to data valid delay
Update rate = 16.7 Hz
Update rate = 10 Hz
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 3.
3 The values of t3 are measured using the load circuit of Figure 2 and are defined as the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is falling edge of SCLK.
5 The PDRST high to data valid delay is typically 1 ms longer than t6 because the internal oscillator requires time to power up and settle.
Circuit and Timing Diagrams
ISINK (1.6mA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
TO
OUTPUT
PIN
50pF
1.6V
ISOURCE (200µA WITH DVDD = 5V,
100µA WITH DVDD = 3V)
Figure 2. Load Circuit for Timing Characterization
PDRST
(INPUT)
DOUT/RDY
(OUTPUT)
t5
Figure 4. Resetting the AD7781
DOUT/RDY
(OUTPUT)
SCLK
(INPUT)
MSB
t3
t1
LSB
t4
t2
Figure 3. Read Cycle Timing Diagram
GAIN OR FILTER
(INPUT)
t6
DOUT/RDY
(OUTPUT)
Figure 5. Changing Gain or Filter Option
Rev. 0 | Page 5 of 16
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