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AD7821

LC2MOS High Speed, μ
P Compatible 8-Bit ADC with Track/Hold Function

Analog Devices 

AD7821

CIRCUIT INFORMATION

BASIC DESCRIPTION

The AD7821 uses a half flash conversion technique (see Func-

tional Block Diagram), whereby two 4-bit flash ADCs are used to

achieve an 8-bit result. Each 4-bit flash ADC contains 15

comparators, which compare an unknown input voltage to the

reference ladder, to achieve a 4-bit result. The MS (most signifi-

cant) flash ADC converts an unknown analog input voltage (VIN)

to provide the 4 MS data bits. An internal DAC, driven by the 4 MS

data bits, then recreates an analog approximation of the input

voltage. The DAC output voltage is subtracted from the analog

input, and the difference is converted by the LS (least significant)

ADC to provide the 4 LS data bits. The MS flash ADC also has one

additional comparator to detect over-range on the analog input.

OPERATING SEQUENCE

The AD7821 has two operating modes. The RD mode allows a con-

version to be started and data to be read with a single, extended,

READ operation (i.e., CS and RD are taken low). The conversion

process is timed out by internal one-shots. The WR-RD mode uses

WR to start a conversion and RD to read the data and allows the

conversion timing to be externally controlled. The operating sequence

for the WR-RD mode is shown in Figure 3.

As a result, the analog input (VIN) of the device can easily be set

up to provide both unipolar and bipolar operation. The data

output code for unipolar and bipolar operation is Natural Binary

and Offset Binary, respectively.

The span of the analog input voltage can easily be varied. By

reducing the reference span, VREF(+) – VREF(–), to less than 5 V,

the sensitivity of the converter can be increased (i.e., if VREF = 2 V

then 1 LSB = 7.8 mV). The reference flexibility also allows the

input span for unipolar operation to be offset from zero (VREF(–) >

GND). Additionally, the input/reference arrangement facilitates

ratiometric operation.

Figures 4 and 5 show some configurations that are possible. For

minimum noise, a 47 µF capacitor in parallel with a 0.1 µF ca-

pacitor should be connected between the reference inputs and

GND.

Figure 4. Power Supply as Reference;

Unipolar Operation (0 to + 5 V)

Figure 3. Operating Sequence (WR-RD Mode)

A conversion is initiated and the analog input signal (VIN) sampled

on the falling edge of WR (falling edge of RD, RD mode). A setup

time (tP, delay time between conversions) of 350 ns is required

prior to this falling edge. See the Digital Interface section for more

details. When WR is low, the internal MS (most significant) ADC

compares the sampled analog input with the reference ladder to

provide the 4 MS data bits. A minimum of 250 ns is required for

this comparison. On the rising edge of WR, the MS data result is

latched internally and the LS (least significant) conversion begins,

to yield the 4 LS data bits. INT goes low typically 380 ns after the

rising edge of WR. This indicates the LS conversion is complete

and that both the LS and MS data results are latched into the

output buffer. RD going low then enables the output data. If a

faster conversion time is required, the RD line can be brought low

250 ns after WR goes high. This latches both the LS and MS

data bits and outputs the conversion result on DB0–DB7.

REFERENCE AND INPUT

The VREF(–) and VREF(+) reference inputs on the AD7821 are

fully differential and define the zero and full-scale input range of

the ADC. The transfer characteristic of the part is defined by

the integer value of the following expression:

Data

(

LSBs

)

=

256



V

V IN

REF (

− V REF (−)

+) − V REF (−

)





+

0.

5

Figure 5. External Reference;

Bipolar Operation (–2.5 V to +2.5 V)

INPUT CURRENT

The analog input of the AD7821 behaves somewhat differently

than conventional ADCs. This is due to the ADC’s sampled

data comparators, which take varying amounts of input current

depending on the cycle of the converter.

The equivalent input circuit of the AD7821 is shown in Figure 6.

When a conversion ends (e.g., falling edge of INT, WR-RD

mode, tRD > tINTL) all the input switches are closed and VIN is

connected to the comparators of the internal LS and MS ADCs.

Therefore, VIN is simultaneously connected to 31 input capacitors

of 1 pF each.

REV. B

–7–

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