AD7933(RevPrG) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
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Lista de partido
AD7933
(Rev.:RevPrG)
(Rev.:RevPrG)
Analog Devices
AD7933 Datasheet PDF : 32 Pages
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Preliminary Technical Data
AD7933/AD7934
TIMING SPECIFICATIONS1
VDD = VDRIVE =2.7 V to 5.25 V, Internal/External VREF = 2.5 V, unless otherwise noted, FCLKIN = 24 MHz, FSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 3.
Parameter
fCLKIN2
Limit at TMIN, TMAX
AD7933 AD7934
10
10
24
24
Unit
kHz
min
MHz
max
tQUIET
10
10
ns min
Description
Minimum time between end of read and start of next conversion, i.e., time from when the
data bus goes into three-state until the next falling edge of CONVST.
t1
10
10
ns min CONVST Pulse Width.
t2
20
20
ns min CONVST Falling Edge to CLKIN Falling Edge Setup Time.
t3
TBD
TBD
ns min CLKIN Falling Edge to BUSY Rising Edge.
t4
0
0
ns min CS to WR Setup Time.
t5
0
0
ns min CS to WR Hold Time.
t6
25
25
ns min WR Pulse Width.
t7
10
10
ns min Data Setup Time before WR.
t8
5
5
ns min Data Hold after WR.
t9
0.5 tCLKIN 0.5 tCLKIN ns min New Data Valid before Falling Edge of BUSY.
t10
0
0
ns min CS to RD Setup Time.
t11
0
0
ns min CS to RD Hold Time.
t12
55
55
ns min RD Pulse Width.
t133
50
50
ns max Data Access Time after RD.
t144
5
5
ns min Bus Relinquish Time after RD.
40
40
ns max Bus Relinquish Time after RD.
t15
15
15
ns min HBEN to RD Setup Time.
t16
5
5
ns min HBEN to RD Hold Time.
t17
10
10
ns min Minimum Time between Reads/Writes.
t18
0
0
ns min HBEN to WR Setup Time.
t19
5
5
ns min HBEN to WR Hold Time.
t20
TBD
TBD
ns min CLKIN Falling Edge to BUSY Rising Edge.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance. See Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode
(W/ = 1), Figure 38, Figure 39, and Figure 40.
2 Mark/space ratio for CLKIN is 40/60 to 60/40.
3 The time required for the output to cross TBD.
4 t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Rev. PrG | Page 7 of 32
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