AD7938BCP Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Lista de partido

AD7938BCP

8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTION

AD7938/AD7939

DB0 1

DB1 2

DB2 3

DB3 4

DB4 5

DB5 6

DB6 7

DB7 8

32 31 30 29 28 27 26 25

PIN 1

IDENTIFIER

AD7938/AD7939

TOP VIEW

(Not to Scale)

24 VIN1

23 VIN0

22 VREFIN/VREFOUT

21 AGND

20 CS

19 RD

18 WR

17 CONVST

9 10 11 12 13 14 15 16

Figure 2. Pin Configuration

Table 5. Pin Function Description

Pin No Mnemonic Function

1 to 8

DB0 to DB7

Data Bits 0 to 7. Three-state parallel digital I/O pins that provide the conversion result and also allow the control

and shadow registers to be programmed. These pins are controlled by CS, RD, and WR. The logic high/low

voltage levels for these pins are determined by the VDRIVE input. When reading from the AD7939, the two LSBs

(DB0 and DB1) are always 0 and the LSB of the conversion result is available on DB2.

9

VDRIVE

10

DGND

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the parallel interface of

the AD7938/AD7939 operates. This pin should be decoupled to DGND. The voltage at this pin may be different

to that at VDD but should never exceed VDD by more than 0.3 V.

Digital Ground. This is the ground reference point for all digital circuitry on the AD7938/AD7939. This pin

should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same

potential and must not be more than 0.3 V apart, even on a transient basis.

11

DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 8, a three-state I/O pin that is controlled

by CS, RD, and WR. When W/B is low, this pin acts as the high byte enable pin. When HBEN is low, the low byte

of data being written to or read from the AD7938/AD7939 is on DB0 to DB7. When HBEN is high, the top four

bits of the data being written to or read from the AD7938/AD7939 are on DB0 to DB3. When reading from the

device, DB4 to DB6 of the high byte contains the ID of the channel to which the conversion result corresponds

(see the channel address bits in Table 9). When writing to the device, DB4 to DB7 of the high byte must be all 0s.

Note that when reading from the AD7939, the two LSBs of the low byte are 0s, and the remaining 6 bits,

conversion data.

12 to 14 DB9 to DB11

15

BUSY

Data Bits 9 to 11. Three-state parallel digital I/O pins that provide the conversion result and also allow the

control and shadow registers to be programmed in word mode. These pins are controlled by CS, RD, and WR.

The logic high/low voltage levels for these pins are determined by the VDRIVE input.

Busy Output. Logic output indicating the status of the conversion. The BUSY output goes high following the

falling edge of CONVST and stays high for the duration of the conversion. Once the conversion is complete and

the result is available in the output register, the BUSY output goes low. The track-and-hold returns to track

mode just prior to the falling edge of BUSY on the 13th rising edge of SCLK, see Figure 35.

16

CLKIN

Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the

AD7938/AD7939 takes 13 clock cycles + t2. The frequency of the master clock input therefore determines the

conversion time and achievable throughput rate. The CLKIN signal may be a continuous or burst clock.

17

CONVST

Conversion Start Input. A falling edge on CONVST is used to initiate a conversion. The track-and-hold goes from track

to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. Following power-

down, when operating in autoshutdown or autostandby modes, a rising edge on CONVST is used to power-up the

device.

18

WR

Write Input. Active low logic input used in conjunction with CS to write data to the internal registers.

19

RD

Read Input. Active low logic input used in conjunction with CS to access the conversion result. The conversion

result is placed on the data bus following the falling edge of RD read while CS is low.

Rev. 0 | Page 9 of 32

Share Link: