AD9267 Ver la hoja de datos (PDF) - Analog Devices
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AD9267 Datasheet PDF : 24 Pages
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AD9267
DIGITAL SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO, CSB, RESET)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (D0±x to D3±x)
ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Low Power, Reduced Signal Option
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temp Min
Full
0.4
Full
Full
−60
Full
−60
Full
Full
Full
1.2
Full
0
Full
−50
Full
−10
Full
Full
Full
1.2
Full
0
Full
−10
Full
+40
Full
Full
Typ
Max
CMOS1/LVDS/LVPECL
0.8
2
450
+60
+60
20
1
DRVDD + 0.3
0.8
−75
+10
30
2
DRVDD + 0.3
0.8
+10
+135
26
5
LVDS
Full
247
Full
1.125
Twos complement
LVDS
Full
150
Full
1.10
Twos complement
454
1.375
250
1.30
Unit
V p-p
mV
μA
μA
kΩ diff
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
mV
V
mV
V
1 For voltage swings beyond the specified range, clamping diodes are recommended.
Rev. 0 | Page 5 of 24
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