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AD9396

Analog/DVI Dual-Display Interface

Analog Devices 

AD9396

2-WIRE SERIAL REGISTER MAP

The AD9396 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to

write and read the control registers through the 2-wire serial interface port.

Table 12. Control Register Map

Hex

Read/Write

Address or Read Only Bits

0x00

Read

[7:0]

0x01

Read/Write

[7:0]

0x02

Read/Write

[7:4]

0x03

Read/Write

[7:6]

[5:3]

[2]

Default

Value

00000000

01101001

1101****

01******

**001***

*****0**

Register Name

Chip Revision

PLL Divider MSB

PLL Divider

VCO Range

Charge Pump

External Clock

Enable

Description

Chip revision ID.

PLL feedback divider value MSB.

PLL feedback divider value.

VCO range.

Charge pump current control for PLL.

Selects the external clock input rather than the internal PLL clock.

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

[7:3] 10000***

[7:0] 10000000

[7:0] 10000000

[7:0] 10000000

[7:0] 00000000

[7:0] 10000000

[7:0] 00000000

[7:0] 10000000

[7:0] 00000000

[7:0] 10000000

[7:0] 00100000

[7:2] 010000**

[7:2] 010000**

[7] 0*******

[6] *0******

[5] **0*****

[4] ***0****

[3] ****0***

[2] *****0**

[1] ******0*

[0] *******0

Phase Adjust

Red Gain

Green Gain

Blue Gain

Red Offset Adjust

Red Offset

Green Offset

Adjust

Green Offset

Blue Offset Adjust

Blue Offset

Sync Separator

Threshold

SOG Comparator

Threshold Enter

SOG Comparator

Threshold Exit

HSYNC Source

HSYNC Source

Override

VSYNC Source

VSYNC Source

Override

Channel Select

Channel Select

Override

Interface Select

Interface Override

Selects the clock phase to use for the ADC clock.

Controls the gain of the red channel PGA. 0 = low gain,

255 = high gain.

Controls the gain of the green channel PGA. 0 = low gain,

255 = high gain.

Controls the gain of the blue channel PGA. 0 = low gain,

255 = high gain.

User adjustment of auto-offset. Allows user control of brightness.

Red offset/target code. 0 = small offset, 255 = large offset.

User adjustment of auto-offset. Allows user control of brightness.

Green offset/target code. 0 = small offset, 255 = large offset.

User adjustment of auto-offset. Allows user control of brightness.

Blue offset/target code. 0 = small offset, 255 = large offset.

Selects the maximum HSYNC pulse width for composite sync

separation.

The enter level for the SOG slicer. Must be less than or equal to the

exit level.

The exit level for the SOG slicer. Must be greater than or equal to

the enter level.

0 = HSYNC.

1 = SOG.

0 = auto HSYNC source.

1 = manual HSYNC source.

0 = VSYNC.

1 = VSYNC from SOG.

0 = auto HSYNC source.

1 = manual HSYNC source.

0 = Channel 0.

1 = Channel 1.

0 = autochannel select.

1 = manual channel select.

0 = analog interface.

1 = digital interface.

0 = auto-interface select.

1 = manual interface select.

Rev. 0 | Page 21 of 48

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