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AD9433

12-Bit, 105 MSPS/125 MSPS IF Sampling A/D Converter

Analog Devices 

AD9433–SPECIFICATIONS

DC SPECIFICATIONS (VDD

=

3.3

V,

VCC

=

5

V;

internal

reference;

◊

differential

encode

input,

unless

otherwise

noted.)

Test AD9433BSQ-105

AD9433BSQ-125

Parameter

Temp Level Min Typ Max

Min Typ Max

Unit

RESOLUTION

12

12

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error1

Differential Nonlinearity (DNL)2

Integral Nonlinearity (INL)2

Full VI

Full VI

25ЊC I

25ЊC I

Full VI

25ЊC I

Full VI

–5

–7

–0.75

–1

–1.0

–1.3

Guaranteed

0

+5

Ϯ1 +3

Ϯ0.25 +0.75

+1

Ϯ0.5 +1.0

+1.3

–5

–7

–0.75

–1

–1.0

–1.3

Guaranteed

0

+5

Ϯ1 +3

Ϯ0.3 +0.75

+1

Ϯ0.5 +1.0

+1.3

mV

% FS

LSB

LSB

LSB

LSB

THERMAL DRIFT

Offset Error

Gain Error1

Reference

Full V

Full V

Full V

–50

–125

± 80

–50

–125

± 80

ppm/ЊC

ppm/ЊC

ppm/ЊC

REFERENCE

Internal Reference Volatge (VREFOUT) Full I

Output Current (VREFOUT)

Full V

Input Current (VREFIN)

Full IV

2.4 2.5 2.6

100

50

2.4 2.5 2.6

V

100

µA

50

µA

ANALOG INPUTS

Differential Input Voltage Range

(AIN, AIN)

Common-Mode Voltage

Input Resistance

Input Capacitance

Analog Bandwidth, Full Power

Full V

Full V

Full VI 2

Full V

Full V

2.0

4.0

3

4

4

750

2.0

4.0

2

3

4

4

750

V

V

kΩ

pF

MHz

POWER SUPPLY

VCC

VDD

Power Dissipation3

Power Supply Rejection Ratio (PSRR)

IVCC2

IVDD2

ENCODE INPUTS

Internal Common-Mode Bias

Differential Input (ENC – ENC)

Input Voltage Range

Input Common-Mode Range

Input Resistance

Input Capacitance

Full IV

Full IV

Full VI

25ЊC I

Full VI

Full VI

Full V

Full V

Full IV

Full IV

Full VI

25ЊC V

4.75 5.0 5.25

2.7

3.3

1275 1425

Ϯ3

255 285

12.5 14

4.75 5.0 5.25

2.7

3.3

1350 1500

Ϯ3

270 300

16 18

V

V

mW

mV/V

mA

mA

3.75

500

–0.5

2.0

6

3

3.75

V

500

mV

VCC + 0.05 –0.5

4.25

2.0

VCC + 0.05 V

4.25

V

6

kΩ

3

pF

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input High Current (VIN = 5 V)

Input Low Current (VIN = 0 V)

Full I

2.0

Full I

0.8

Full V

50

Full V

50

2.0

V

0.8

V

50

µA

50

µA

DIGITAL OUTPUTS

Logic “1” Voltage

Logic “0” Voltage

Output Coding

Full VI

VDD – 0.05

Full VI

0.05

VDD – 0.05

V

0.05

V

Two’s Complement or Offset Binary

NOTES

1Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).

2SFDR disabled (SFDR = GND) for DNL and INL specifications.

3Power dissipation measured with rated encode and a dc analog input (Outputs Static, I VDD = 0). IVCC and IVDD measured with 10.3 MHz analog input @ –0.5 dBFS.

Specifications subject to change without notice.

–2–

REV. 0

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