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AD9434-370EBZ

14-Bit 105/125 MSPS A/D Converter

Analog Devices 

Data Sheet

AD9434

Timing Diagrams

N–1

VIN+, VIN–

tCH

CLK+

CLK–

DCO+

DCO–

Dx+

Dx–

tA

N

N+1

tCL

1/fS

N+2

N+3

tCPD

tSKEW

tPD

N – 15

N – 14

N – 13

Figure 2. Single Data Rate Mode

N+4

N+5

N – 12

N – 11

VIN+, VIN–

CLK+

CLK–

DCO+

DCO–

D0/D6+

D0/D6–

D5/D11+

D5/D11–

N–1

tA

N

tCH

tCL

N+1

1/fS

N+2

N+3

N+4

N+5

tCPD

tSKEW

tPD

D6

N – 15

D0

N – 14

D6

N – 14

D0

N – 13

D6

N – 13

D0

N – 12

D6

N – 12

D0

N – 11

D6

N – 11

D0

N – 10

D11

N – 15

D5

N – 14

6 LSBs

D11

N – 14

6 MSBs

D5

N – 13

D11

N – 13

Figure 3. Double Data Rate Mode

D5

N – 12

D11

N – 12

D5

N – 11

D11

N – 11

D5

N – 10

Rev. B | Page 7 of 28

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