AD9511BCPZ Ver la hoja de datos (PDF) - Analog Devices

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Lista de partido

AD9511BCPZ

1.2Ghz Clock Distribution IC / PLL Core / Divider / Delay Adjust / 8 Outputs

Analog Devices 

AD9511

Parameter

DELAY ADJUST

Shortest Delay Range4

Zero Scale

Full Scale

Linearity, DNL

Linearity, INL

Longest Delay Range4

Zero Scale

Full Scale

Linearity, DNL

Linearity, INL

Delay Variation with Temperature

Long Delay Range, 10 ns5

Zero Scale

Full Scale

Short Delay Range, 1 ns5

Zero Scale

Full Scale

Min Typ

0.05 0.36

0.72 1.12

0.5

0.8

0.20 0.57

9.0 10.2

0.3

0.6

Max Unit Test Conditions/Comments

OUT4; LVDS and CMOS

35h <5:1> 11111b

0.68 ns

36h <5:1> 00000b

1.51 ns

36h <5:1> 11111b

LSB

LSB

35h <5:1> 00000b

0.95 ns

36h <5:1> 00000b

11.6 ns

36h <5:1> 11111b

LSB

LSB

0.35

−0.14

0.51

0.67

ps/°C

ps/°C

ps/°C

ps/°C

1 The measurements are for CLK1. For CLK2, add approximately 25 ps.

2 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.

3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

4 Incremental delay; does not include propagation delay.

5 All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. A | Page 8 of 60

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