AD9726BSVZ Ver la hoja de datos (PDF) - Analog Devices

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AD9726BSVZ

16-Bit, 400 MSPS Digital-to-Analog Converter

Analog Devices 

AD9726

DIGITAL SIGNAL SPECIFICATIONS

DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference,

TMIN to TMAX, unless otherwise specified.

Table 3.

Parameter

DAC CLOCK INPUTS (CLK±)

Differential Voltage

Common-Mode Voltage

LVDS INPUTS (DB[15:0]±, DCLK_IN±)

Input Voltage Range

Differential Threshold Voltage

Differential Input Impedance

LVDS OUTPUT (DCLK_OUT±)

Differential Output Voltage1

Offset Voltage

Short-Circuit Output Current

CMOS INPUTS (CSB, SCLK, SDIO, RESET)

Logic 0 Voltage

Logic 1 Voltage

Input Current

CMOS OUTPUTS (SDO, SDIO)

Logic 0 Voltage

Logic 1 Voltage

Short-Circuit Output Current

CONTROL INPUTS (SPI_DIS, SDR_EN)

Logic 0 Voltage

Logic 1 Voltage

Input Current

Min

Typ

Max

Unit

0.5

1.0

V

1.0

1.25

V

825

1575

mV

100

mV

100

Ω

250

400

mV

1.0

1.2

V

20

mA

0.5

V

2.5

V

1

nA

0.5

V

3.0

V

10

mA

0.5

V

2.0

V

1

nA

1 With 100 Ω external load.

TIMING SPECIFICATIONS

DBVDD = AVDD1 = AVDD2 = 3.3 V, DVDD = CLKVDD = ADVDD = ACVDD = 2.5 V, IOUT-FS = 20 mA, internal reference,

TMIN to TMAX, unless otherwise specified.

Table 4.

Parameter

LVDS DATA BUS

Data Synchronization Enabled (Default)

DDR DCLK_OUT± Propagation Delay (tDCPD-DDR)

DDR DB[15:0]± Setup Time (tDSU-DDR)

DDR DB[15:0]± Hold Time (tDH-DDR)

SDR DCLK_OUT± Propagation Delay (tDCPD-SDR)

SDR DB[15:0]± Setup Time (tDSU-SDR)

SDR DB[15:0]± Hold Time (tDH-SDR)

Data Synchronization Bypassed

DB[15:0]± Setup Time (tDSU-BYPASS)

DB[15:0]± Hold Time (tDH-BYPASS)

CLK± to IOUT Propagation Delay (tPD-BYPASS)

DB[15:0]± to IOUT Pipeline Delay (tPIPE-BYPASS)

Min

Typ

Max

Unit

−100

500

−100

500

2000

ps

ps

ps

300

ps

ps

ps

800

50

0.85

4

ps

ps

ns

DAC clock cycles

Rev. B | Page 5 of 24

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