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EVAL-ADF4193EB1
(Rev.:RevB)

Low Phase Noise, Fast Settling PLL Frequency Synthesizer

Analog Devices 

ADF4193

Phase Look-Up Table

The ADF4193’s fast lock sequence is initiated following the

write to Register R0. The fast lock timers are programmed so

that after the PLL has settled in wide BW mode, the charge

pump current is reduced and loop filter resistor switches are

opened to reduce the loop BW. The reference cycle on which

these events occur is determined by the values preprogrammed

into the timeout counters.

Figure 10 and Figure 13 show that the lock time to final phase is

dominated by the phase swing that occurs when the BW is

reduced. Once the PLL has settled to final frequency and phase,

in wide BW mode, this phase swing is the same, regardless of

the size of the synthesizer’s frequency jump. The amplitude of

the phase swing is related to the current flowing through the

loop filter zero resistors on the PFD reference cycle that the

SW1/SW2 switches are opened. In an integer-N PLL, this

current is zero once the PLL has settled. In a fractional-N PLL,

the current is zero on average but varies from one reference

cycle to the next, depending on the quantization error sequence

output from the digital Σ-Δ modulator. Because the Σ-Δ

modulator is all digital logic, clocked at the PFD reference rate,

for a given value of MOD, the actual quantization error on any

given reference cycle is determined by the value of FRAC and

the PHASE word that the modulator is seeded with, following

the write to R0. By choosing an appropriate value of PHASE,

corresponding to the value of FRAC, that is programmed on the

next write to R0, the size of the error current on the PFD

reference cycle the SW1/SW2 switches opened, and thus the

phase swing that occurs when the BW is reduced can be

minimized.

With dither off, the fractional spur pattern due to the SDM’s

quantization noise also depends on the phase word the modulator

is seeded with. Tables of optimized FRAC and phase values for

popular SW1/SW2 and ICP timer settings can be down-loaded

from the ADF4193 product page. If making use of a phase table,

first write phase to double buffered Register R2, then write the

INT and FRAC to R0.

Avoiding Integer Boundary Channels

A further option when programming a new frequency involves

a write to Register R1 to avoid integer boundary spurs. If it is

found that the integer boundary spur level is too high, an

option is to move the integer boundary away from the desired

channel by reprogramming the R divider to select a different

PFD frequency. For example, if REFIN = 104 MHz and R = 4 for

a 26 MHz PFD reference and MOD = 130 for 200 kHz steps, the

frequency channel at 910.2 MHz has a 200 kHz integer

boundary spur because it is 200 kHz offset from 35 × 26 MHz.

An alternative way to synthesize this channel is to set R = 5 for a

20.8 MHz PFD reference and MOD = 104 for 200 kHz steps.

The 910.2 MHz channel is now 5 MHz offset from the nearest

integer multiple of 20.8 MHz and the 5 MHz beat note spurs are

well attenuated by the loop. Setting double buffered Bit R1 [23] = 1

(CP ADJ bit) increases the charge pump current by 25%, which

compensates for the 25% increase in N with the change to the

20.8 MHz PFD frequency. This maintains constant loop

dynamics and settling time performance for jumps between the

two PFD frequencies. The CP ADJ bit should be cleared again

when jumping back to 26 MHz-based channels.

The Register R1 settings necessary for integer boundary spur

avoidance are all double buffered and do not become active on

the chip until the next write to Register R0. Register R0 should

always be the last register written to when programming a new

frequency.

Serial Interface Activity

The serial interface activity when programming the R2 or R1

registers causes no noticeable disturbance to the synthesizers

settled phase or degradation in its frequency spectrum.

Therefore, in a GSM application, it can be performed during

the active part of the data burst. Because it takes just 10.2 μs to

program the three registers, R2, R1, and R0, with the 6.5 MHz

serial interface clock rate typically used, this programming can

also be performed during the previous guard period with the

LE edge to latch in the R0 data delayed until it’s time to switch

frequency.

Rev. B | Page 24 of 28

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